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datasheet 5pb12xx july 11, 2016 1 ?2015 integrated device technology, inc. 3-channel high-performance tcxo/lvcmos clock buffer family 5pb12xx description the 5pb12xx is a high-perfo rmance tcxo/lvcmos clock fanout buffer family with individual oe pin for each output. the clkin pin can accept eit her a square wave (lvcmos) or clipped sine wave (such as tcxo clipped sine wave output) as input. there are 3 different fan-out versions available: 1:3, 1:4 and 1:6. the 5pb12xx has industry-leading low jitter and extremely low current consumption, making it ideal for smart mobile devices. applications ? smart mobile handsets ? rf and baseband peripheral clock distribution ? automotive features ? extremely low operating and standby current consumption ? low rms additive phase jitter ? family supports 1.8v to 3.3v power supply voltage: ? for 1.8v supply: 5pb1203, 5pb1204, 5pb1206 ? for 2.5v / 3.3v supply: 5pb1213, 5pb1214, 5pb1216 ? three, four, and six outputs with individual output enable pin ? one input ? oe_osc control pin to enabl e/disable reference tcxo/xo ? small 10-pin, 16-pin and 20-pin packages available ? industrial -40o to +105oc temperature range block diagram clkout1 clkin clkout2 clkout6 control logic oe1 oe2 oe6 oe_osc
3-channel high-performance tcxo/lvc mos clock buffer family 2 july 11, 2016 5pb12xx datasheet pin assignments pin descriptions 1 2 3 4 5 6 7 8 9 10 5pb1203 / 5pb1213 10-pin 2mm x 2mm dfn gnd vdd clkin oe_osc oe3 oe1 oe2 clkout3 clkout2 clkout1 ? 5pb1204 / 5pb1214 16-pin, 2.5mm x 2.5mm vfqfpn 8xxxxxx oe3 gnd v dd oe2 2 3 4 1 12 11 10 9 16 15 14 13 oe1 clkin clkout1 gnd gnd clkout3 clkout2 v dd clkout4 5678 oe4 oe_osc v dd ? 5pb1206 / 5pb1216 20-pin, 3mm x 3mm vfqfpn clkout5 gnd clkout4 clkout3 v dd oe4 oe5 oe_osc v dd clkout6 678910 20 19 18 17 16 clkin oe1 clkout2 clkout1 gnd oe6 gnd v dd oe3 oe2 2 3 4 5 115 14 13 12 11 5pb1203 5pb1213 5pb1204 5pb1214 5pb1206 5pb1216 vdd 2 2, 7, 12 3, 9, 15 power connect 1.8v to 5pb1203/5pb1204/5pb1206. connect 2.5v or 3.3v to 5pb1213/5pb1214/5pb1216. gnd 1 3, 9, 14 4, 12, 18 power power supply ground. clkin 3 15 20 input reference input pin. connect to lvcmos input or tcxo. oe_osc 4 6 8 output input crystal oscillator enable pin. follow enable function truth table. if all oe pins are low then oe_osc is low. otherwise oe_osc is high, enabling reference crystal oscillator. oe1 6 16 19 input output enable pin for clkout1. active high. internal 120k ? pull-down. oe2 7 1 1 input output enable pin for clkout2. active high. internal 120k ? pull-down. oe3 5 4 2 input output enable pin for clkout3. active high. internal 120k ? pull-down. oe4 ? 5 6 input output enable pin for clkout4. active high. internal 120k ? pull-down. oe5 ? ? 7 input output enable pin for clkout5. active high. internal 120k ? pull-down. oe6 ? ? 5 input output enable pin for clkout6. active high. internal 120k ? pull-down. clkout1 8 13 17 output clock output 1. same frequency as clkin. clkout2 9 11 16 output clock output 2. same frequency as clkin. clkout3 10 10 14 output clock output 3. same frequency as clkin. clkout4 ? 8 13 output clock output 4. same frequency as clkin. clkout5 ? ? 11 output clock output 5. same frequency as clkin. clkout6 ? ? 10 output clock output 6. same frequency as clkin. pin name pin number pin type pin description
july 11, 2016 3 3-channel high-perform ance tcxo/lvcmos clock buffer family 5pb12xx datasheet enable function truth table external components a minimum number of external components are required for proper operation. a decoupling capacitor of 0.01 f should be connected between vdd on pin 1 and gnd on pin 4, as close to the device as possible. a 33 ? series terminat ing resistor may be used on each clock output if the trace is longer than 1 inch. to achieve the low output skew that the 5pb12xx is capable of, ca reful attention must be paid to board layout. essentially, all four outputs must have identica l terminations, identical loads and identical trace geometries. if they do not, the output skew will be degraded. for example, using a 30 ? series termination on one output (with 33 ? on the others) will cause at le ast 15 ps of skew. absolute maximum ratings stresses above the ratings listed below ca n cause permanent damage to the 5pb12xx. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specific ations is not implied. exposure to absolute maximum rating conditions for extended periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. item rating supply voltage, vdd 3.465v output enable and all inputs /outputs -0.5 v to vdd+0.5 v ambient operating temperature (extended) -40 to +105 ? c storage temperature -65 to +150 ? c junction temperature 125 ? c soldering temperature 260 ? c oe1 oe2 oe3 oe4 oe5 oe6 oe_osc clkout1 clkout2 clkout3 clkout4 clkout5 clkout6 0 0 0 0 0 0 0 hi-z hi-z hi-z hi-z hi-z hi-z 1 0 0 0 0 0 1 clock hi-z hi-z hi-z hi-z hi-z 1 1 0 0 0 0 1 clock clock hi-z hi-z hi-z hi-z ????????????? 1 1 1 1 1 1 1 clock clock clock clock clock clock input output
3-channel high-performance tcxo/lvc mos clock buffer family 4 july 11, 2016 5pb12xx datasheet dc electrical characteristics (vdd = 1.8v, 2.5v, 3.3v) vdd=1.8v 5% , ambient temperature -40 to +105c, unless stated otherwise vdd=2.5 v 5% , ambient temperature -40 to +105c, unless stated otherwise parameter symbol conditions min. typ. max. units operating voltage vdd 1.7 1.9 v input high voltage, clkin v ih lvcmos input. note 1 0.7xvdd vdd v input low voltage, clkin v il lvcmos input. note 1 0.3xvdd v input high voltage, oe v ih 0.7xvdd vdd v input low voltage, oe v il 0.3xvdd v output high voltage v oh i oh = -4ma 0.8xvdd v output low voltage v ol i ol = 4ma 0.2xvdd v nominal output impedance z o 17 ? input capacitance c in 5pf operating supply current 5pb1203 idd clkin=26mhz, all outputs enabled 5.10 ma clkin=low or high, all outputs disabled 0.02 0.03 5pb1204 clkin=26mhz, all outputs enabled 8.30 clkin=low or high, all outputs disabled 2.51 2.52 5pb1206 clkin=26mhz, all outputs enabled 11.90 clkin=low or high, all outputs disabled 2.5 2.6 parameter symbol conditions min. typ. max. units operating voltage vdd 2.375 2.625 v input high voltage, clkin v ih lvcmos input. note 1 0.7xvdd vdd v input low voltage, clkin v il lvcmos input. note 1 0.3xvdd v input high voltage, oe v ih 0.7xvdd vdd v input low voltage, oe v il 0.3xvdd v output high voltage v oh i oh = -4ma 0.8xvdd v output low voltage v ol i ol = 4ma 0.2xvdd v nominal output impedance z o 17 ? input capacitance c in iclk, oe pin 5 pf operating supply current 5pb1213 idd clkin=26mhz, all outputs enabled 6.68 ma clkin=low or high, all outputs disabled 0.05 0.31 5pb1214 clkin=26mhz, all outputs enabled 10.2 clkin=low or high, all outputs disabled 3.47 3.47 5pb1216 clkin=26mhz, all outputs enabled 16.5 clkin=low or high, all outputs disabled 3.50 3.60
july 11, 2016 5 3-channel high-perform ance tcxo/lvcmos clock buffer family 5pb12xx datasheet vdd=3.3 v 5% , ambient temperature -40 to +105c, unless stated otherwise notes: 1. nominal switching threshold is vdd/2 parameter symbol conditions min. typ. max. units operating voltage vdd 3.15 3.45 v input high voltage, clkin v ih lvcmos input. note 1 0.7xvdd vdd v input low voltage, clkin v il lvcmos input. note 1 0.3xvdd v input high voltage, oe v ih 0.7xvdd vdd v input low voltage, oe v il 0.3xvdd v output high voltage v oh i oh = -4ma 0.8xvdd v output low voltage v ol i ol = 4ma 0.2xvdd v nominal output impedance z o 17 ? input capacitance c in iclk, oe pin 5 pf operating supply current 5pb1213 idd clkin=26mhz, all outputs enabled 9.10 ma clkin=low or high, all outputs disabled 0.22 0.25 5pb1214 clkin=26mhz, all outputs enabled 13.4 clkin=low or high, all outputs disabled 4.28 4.45 5pb1216 clkin=26mhz, all outputs enabled 21.4 clkin=low or high, all outputs disabled 4.60 5.60
3-channel high-performance tcxo/lvc mos clock buffer family 6 july 11, 2016 5pb12xx datasheet ac electrical characteristics (vdd = 1.8v, 2.5v, 3.3v) vdd = 1.8v 5% , for 5pb1203 / 1204 / 1206 , ambient temperature -40 to +105c, unless stated otherwise vdd = 2.5 v 5% , for 5pb1213 / 1214 / 1216 , ambient temperature -40 to +105c, unless stated otherwise parameter symbol conditions min. typ. max. units input frequency 0 200 mhz output rise time t or 0.36 to 1.44 v, c l =5 pf 0.6 1.0 ns output fall time t of 1.44 to 0.36 v, c l =5 pf 0.6 1.0 ns propagation delay note 1 note 1 2.5 3 3.5 ns buffer additive phase jitter, rms 26m hz tcxo clipped sine wave input, integration range: 12khz to 20mhz 420 fs 125mhz lvcmos input, integration range: 12khz to 20mhz 42 fs output to output skew t skewo ? o note 2, rising edges at vdd/2 50 65 ps device to device skew t skewd-d rising edges at vdd/2 200 ps delay for output enable / disable time enablex to bclkn t en/ t dis cl < 5 pf 3 cycles start-up time t start-up 2ms tcxo clock clipped sine wave input voltage swing level vin pp vdd = 1.8v, should connect to clkin through ac coupling and bias circuit 0.8 v parameter symbol conditions min. typ. max. units input frequency 0 200 mhz output rise time t or 0.5 to 2.0 v, c l =5 pf 0.6 1.0 ns output fall time t of 2.0 to 0.5 v, c l =5 pf 0.6 1.0 ns propagation delay note 1 note 1 3 3.5 4 ns buffer additive phase jitter, rms 26m hz tcxo clipped sine wave input, integration range: 12khz to 20mhz 280 fs 125mhz lvcmos input, integration range: 12khz to 20mhz 30 fs output to output skew t skewo ? o note 2, rising edges at vdd/2 40 65 ps device to device skew t skewd-d rising edges at vdd/2 200 ps delay for output enable / disable time enablex to bclkn t en/ t dis cl < 5 pf 3 cycles start-up time t start-up part start-up time for valid outputs after vdd ramp-up 2ms tcxo clock clipped sine wave input voltage swing level vin pp vdd = 2.5v, should connect to clkin through ac coupling and bias circuit 0.8 v
july 11, 2016 7 3-channel high-perform ance tcxo/lvcmos clock buffer family 5pb12xx datasheet vdd = 3.3 v 5% , for 5pb1213 / 1214 / 1216 , ambient temperature -40 to +105c, unless stated otherwise notes: 1. with rail to rail input clock 2. between any 2 outputs with equal loading. 3. duty cycle on outputs will match incoming clock duty c ycle. consult idt for tight duty cycle clock generators. test load and circuit ac coupling and bias circuit parameter symbol conditions min. typ. max. units input frequency 0 200 mhz output rise time t or 0.5 to 2.0 v, c l =5 pf 0.6 1.0 ns output fall time t of 2.64 to 0.66 v, c l =5 pf 0.6 1.0 ns propagation delay note 1 note 1 2.5 3 3.5 ns buffer additive phase jitter, rms 26m hz tcxo clipped sine wave input, integration range: 12khz to 20mhz 377 fs 125mhz lvcmos input, integration range: 12khz to 20mhz 18 fs output to output skew t skewo ? o note 2, rising edges at vdd/2 25 65 ps device to device skew t skewd-d rising edges at vdd/2 200 ps delay for output enable / disable time enablex to bclkn t en/ t dis cl < 5 pf 3 cycles start-up time t start-up part start-up time for valid outputs after vdd ramp-up 2ms tcxo clock clipped sine wave input voltage swing level vin pp vdd = 3.3v, should connect to clkin through ac coupling and bias circuit 0.5 v rs=33ohm 5 i n c h e s cl = 5pf 50ohms r1 c1 r2 tcxo idt 5pb12xx vdd vdd component value c1 1f r1 10k r2 10k
3-channel high-performance tcxo/lvc mos clock buffer family 8 july 11, 2016 5pb12xx datasheet package outline and dimensions (5pb1203 / 5pb1213 10-pin dfn)
july 11, 2016 9 3-channel high-perform ance tcxo/lvcmos clock buffer family 5pb12xx datasheet package outline and dimensions (5pb1203 / 5pb1213 10-pin dfn), cont.
3-channel high-performance tcxo/lvcmo s clock buffer family 10 july 11, 2016 5pb12xx datasheet package outline and dimensions (5pb1204 / 5pb1214 16-pin vfqfpn)
july 11, 2016 11 3-channel high-performance tcxo/l vcmos clock buffer family 5pb12xx datasheet package outline and dimensions (5pb1204 / 5pb1214 16-pin vfqfpn), cont.
3-channel high-performance tcxo/lvcmo s clock buffer family 12 july 11, 2016 5pb12xx datasheet package outline and dimensions (5pb1206 / 5pb1216 20-pin vfqfpn), use epad option p2
july 11, 2016 13 3-channel high-performance tcxo/l vcmos clock buffer family 5pb12xx datasheet package outline and dimensions (5pb1206 / 5pb1216 20-pin vfqfpn), cont. epad option 1.65mm
3-channel high-performance tcxo/lvcmo s clock buffer family 14 july 11, 2016 5pb12xx datasheet ordering information ?g? after the two-letter package code denotes pb-free configuration, rohs compliant. marking diagrams notes: 1. ? ** ? is the lot number. 2. ?yww?, ?yw?, or ?y? are the last digit(s) of the year and week that the part was assembled. 3. ?$? denotes mark code. 4. ?k? denotes extended temperature range device. 5. ?xxx? denotes last three characters of asm lot. revision history rev. date originator description of change a 07/11/16 h.g. release to final. part / order number shipping packaging package temperature 5pb1203ntgk cut tape 10-pin dfn -40 to +105c 5pb1203ntgk8 tape and reel 10-pin dfn -40 to +105c 5pb1213ntgk cut tape 10-pin dfn -40 to +105c 5pb1213ntgk8 tape and reel 10-pin dfn -40 to +105c 5pb1204cmgk cut tape 16-pin vfqfpn -40 to +105c 5pb1204cmgk8 tape and reel 16-pin vfqfpn -40 to +105c 5pb1214cmgk cut tape 16-pin vfqfpn -40 to +105c 5pb1214cmgk8 tape and reel 16-pin vfqfpn -40 to +105c 5PB1206NDGK tube 20-pin vfqfpn -40 to +105c 5PB1206NDGK8 tape and reel 20-pin vfqfpn -40 to +105c 5pb1216ndgk tube 20-pin vfqfpn -40 to +105c 5pb1216ndgk8 tape and reel 20-pin vfqfpn -40 to +105c 203k yw** 10-pin dfn 213k yw** 10-pin dfn 204k y** 16-pin vfqfpn 214k y** 16-pin vfqfpn xxx yww$ 206k 20-pin vfqfpn xxx yww$ 216k 20-pin vfqfpn
disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or specifications d escribed herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice. performance spe cifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information co ntained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limi ted to, the suitab ility of idt?s products for any particular purpose, an implied war ranty of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third pa rties. idt?s products are not intended for use in applications involvin g extreme environmental conditions or in life support systems o r similar devices where the failure or malfun ction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. product specification subject to change wi thout notice. other trademarks and service marks used herein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright ?2015 integrated device technology, inc.. all rights reserved. corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa www.idt.com sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com/go/sales tech support www.idt.com/go/support

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